What simulations tools do you recommend?

Generally, simulation tools do the same thing but each has its own limitations. The accuracy of the SI or PI analysis lies in the specialist's knowledge of the limitations of these simulators. For example, one cannot simulate a tapered waveguide with crosssection width varying in the direction of the wave propagation with a 2.5D layout solver like Siwave or Hyperlynx SI while expecting accurate results. On the other hand, a cannon should not be used to kill a mosquito; we do not want to calculate a stripline impedance with a 3D full wave solver for example. Here is a list of tools we think they are most suited for the analyses below.

 

Trace Impedance Calculation:

• Polar Si8000 quick solver
• Hyperlynx 2D Wavessolver
• Keysight ADS Controlled Impedance Designer

• Protoexpress (Free and surprisingly accurate)

Crosstalk Constraints:

• Hyperlynx 2D Wavessolver
• Keysight ADS

Structure Optimizations (Vias transistions, Connectors, voids under SMD pads ... etc.):

• ANSYS HFSS
• ANSYS HFSS 3D Layout

Topology Simulation (Schematic tools):

• Keysight ADS Schematic
• Hyperlynx Freeform schematic

Post layout channel extractions:

• ANSYS HFSS 3D Layout (The most precise)
• Hyperlynx SI (when speed is preferred over accuracy)

PCB and IC Package Layout Reviews

• Hyperlynx DRC

High Speed Interface Compliance:

• Hyperlynx SI (SerDes and DDR Wizards)

Power Plane Extraction (for PCB and IC Package)

• ANSYS Siwave

 

Please visit the knowledge base page linked below for detailed comparisons between simulators

Can I download ANSYS for free?

Ansys Student gives you the tools you’ll use in your future careers. Learn the fundamentals of simulation while gaining experience using our state-of-the-art Ansys Workbench simulation workflow.

Can I download Keysight ADS for free?

For students, licenses are granted based on the agreement with your university. For Individuals, you may request a free trial license from Keysight ADS website.

What is your signal integrity analysis methodology for high speed digital PCBs?

At Teramesh, we implement a Shift Left SI design methodology. We believe the value of the Signal Integrity Analysis increases when it is done sooner in the deisgn phase. Therefore, we conclude a set of design constraints that guides the layout design process to ensure the first attempt of the PCB layout meets the required SI performance. The summary of this SI analysis is shown below:

• PCB Material: Import an accurate material model (Dielectric properties and copper foil parameters), capture frequency dependence of dielectric parameters, as well as copper roughness.

• Transmission Line Design: Calculate trace width and spacing for the required impedances, as well as the trace-to-trace separation for the required isolation performance using a 2D FEM solver like Polar Si8000 or Hyperlynx 2D Field solver or ADS Controlled Impedance designer. Capture fabrication imperfections like etch-factor, solder mask conformality, and copper or dielectric layer thickness tolerances to know the maximum/minimum impedance variation you will have. Revise your results with the manufacturer.

• 3D Optimizations: High speed channel discontinuity optimization (Via transitions, connectors, SMD components ... etc.) using a 3D FEM tool like ANSYS HFSS.

• Insertion loss budgeting for SerDes channels (to devise the maximum routing length).

• Prelayout topology simulation in a schematic tool like Keysight ADS or Hyperlynx or ANSYS circuit

Then the constraints are communicated to the layout desiner

• Post layout S-parameter extractions (Using HFSS 3D Layout) when the design constraints are  marginalised or violated (case by case).

Through shifting the bulk of the SI analysis to the prelayout phase, faster design cycles can be achieved as well as less 3D FEA software license utilisation. The details of each step are explained in the link below.

What Power Integrity Analysis should I do before approving my ASIC silicon and package designs?

Teramesh recommends verifying the voltage drop from the voltage regulator module (VRM) to the load (the ASIC's or FPGA's silicon) meets the IP specification across all frequencies. The following analyses are the minimum the PI designer should check for:

• Static IR-drop DC analysis with the ASIC package and PCB power planes (ANSYS Siwave or Cadence Sigrity have a straight forward flow). This will identify fundamental failures (like higher than optimal current density, less BGAs for a high current rail) if exist.
• PDN Impedance - small signal AC analysis 
  (start by extracting the N-port S-parameters of the power planes with a tool like Siwave, then run an AC current frequency sweep with one active supply only at a time to visualise the PDN impedance (Z = V / I) and improve to suppress any high resonance.
• Isolation between voltage rails or with  sensitive signals - small signal AC analysis (start by extracting the N-port S-parameters of the power planes and sensitive RF or clock nets passing close to the planes with a tool like Siwave, then run an AC current frequency sweep with one active supply only at a time to visualise the isolation between different power rails). If a voltage ripple peak appeared at current load A while sweeping voltage source B, there might be an isolation problem between the two rails. Apply the worst case excitation for the sensitive signals and assess the induced ripple to the power planes.
• Dynamic IR drop transient analysis with the ASIC package and PCB power planes S-parameter extraction, and the time-domain current profile models (CPM) of each load current in the ASIC for slow ripples (<100 MHz) and fast ripples (>100MHz). Collaboration between the ASIC deisgner, ASIC package designer, the PCB layout engineer, and the PI specialist is crucial for the accuracy of this simulation.

For details about each of the aforementioned analyses, pleae read the article linked below in our knowledge base.