Power Integrity Analysis:
from the Voltage Regulator Module to the Die 

The purpose of this article is to give the reader an idea about Teramesh's methodology for carrying out power integrity (PI) analysis for the power distribution network (PDN) between the voltage regulator module (VRM) and the application specific integrated circuit (ASIC) or FPGA device. The article details the minimum analyses and simulations we do to ensure clean power rails at the ASIC's current sinks on the die.

The Goal of the Power Integrity Analysis

With the rapid development of technology, the design of a proper PDN becomes more challenging due to lower supply voltage, faster switching frequencies, and higher current variations. Thus, the adoption of an efficient PI simulation methodology becomes a necessity to decrease DC IR drop as well as the AC impedance of the PDN from the VRM to the Die. The goal of the PI analysis is to ensure that the PDN impedance does not give rise to undesired DC IR drop or AC ripple at the current sink of the ASIC (at the die).

Teramesh's approach to power integrity verificaiton is to find the worst case noise ripple from both the frequency domain analysis and the time domain analysis, and optimize the PDN such that both analyses meet the ripple specification set by the IP designer. Therefore, the minimum PI analyses Teramesh does for any ASIC project are outlined below:

1. Static (DC) IR drop and current density analysis

2. AC Harmonic Analyses:

   1. PDN impedance and resonance suppression

   2. Isolation between voltage rails and sensitive signals

3. Dynamic IR drop transient analysis

The following sections detail the aforementioned steps and show real-case scenarios from our previous projects.

The PDN Ecosystem

The PDN consists of all the interconnects from the VRM to the power rails on the die. All elements along this path have a role in delivering a clean, low-noise voltage supply to the power rails on the die. The frequency domain is a convenient perspective to analyse the PDN since specific elements of the PDN dominate the impedance behaviour in certain frequency regions [1]. The interaction between these elements is what gives rise to resonances which amplify the power rail noise, causing high ripple voltage at the load, which can make a design fail. The PI designer needs to analyse the PDN with all components in place to capture this interaction-induced behaviour, and those components need to be modeled accurately to avoid not meeting the noise specification or overdesigning.

Components Models

Accurate simulation results that precisely match lab measurements cannot be obtained without precise models for each component in the PDN system that capture all influential device effects. At the end of the day, simulators do what we tell them to do.

Voltage Regulator Module

When modeling the PDN, the VRM is the major component in supplying power to the load. It serves as the key power conversion element, transforming an input voltage into the DC voltages needed by the current consumers. There are two main types of VRMs: linear and switching. While linear regulators are simpler, cheaper, less noisy, and easier to model, they operate with low conversion efficiency, which makes them unfit for high-current applications. Switchers, on the other hand, are known to be more efficient, yet they require more care in their design to maintain adequate noise performance and stability. Although the VRM dominate the PDN impedance performance in the low-frequency region (~ tens of KHz), as mentioned before in this article, the interaction between PDN components gives rise to resonances outside their range of dominance, and that is what makes the accurate modelling of the VRM crucial for PDN analysis even if the current sinks switch at much higher speeds.

The simplest form of the VRM model is the ideal voltage source in any spice simulator with a series output resistor (the resistor model), which tells the simulator to bypass the VRM's AC behavior. Such representation models a wrong VRM impedance and none of its nonidealities. Next, a classical first-order resistance-inductance (R-L) model can represent the VRM impedance over frequency to a fair extent. Higher-order models that consist of multiple resistance-inductance (and maybe capacitance) elements can better fit the actual impedance of the VRM. Nevertheless, the model still does not provide any information about the device's power supply rejection ratio (PSRR), bandwidth, stability, or switching noise [2].

Accurate VRM models that reflect the non-linear properties of the switching transistors and feedback loops are needed to explore the device switching noise performance, PSRR, stability, and other metrics that cannot be linearized, especially when analyzing large current signals. Full transistor-level models of all the power supply circuitry are too complicated for efficient simulation times and usually cannot be shared by the vendor. Therefore, a measurement or datasheet-based behavioral model is needed to simulate the VRM in the PDN ecosystem in a reasonable time. State space average modeling (SSAM) was first introduced in the 1970s [3]. These are behavioral models that average the states of the SMPS, effectively smoothing out the switching behaviour and focusing on the AC behavior of the control loop [4]. 

Sandler's SSAM is a behavioral model that simulates all noise sources going into and out of the SMPS [3]. The model averages the power switch states to determine the behavior, and it supports different operation modes (continuous conduction, discontinuous conduction, current, and voltage modes), which makes it a universal model. Sandler's SSAM assumes the regulator is running at a switching frequency at least six times higher than the control loop bandwidth. The model works well for small and large current signals and can be used for single and multi-phase VRMs. Sandler's model is available in a Keysight workspace format and can be downloaded and used directly.

Decoupling Capacitors

Ideal capacitors are theoretical components that provide perfect charge storage and instantaneous current delivery, with no resistance, inductance, or frequency-dependent behavior. However, actual capacitors exhibit non-idealities such as equivalent series resistance (ESR) and equivalent series inductance (ESL), affecting their performance. Dielectric properties, DC bias effects, and temperature variations further impact the actual capacitance value during operation. Capacitor vendors like Murata and Kemet often offer detailed charts for the relevant parameters to model the capacitor's non-idealities. The power integrity designer should be aware of the measurement technique the vendor used to utilize values from these charts appropriately. For example, Murata states that the frequency response of capacitors is measured by a network analyzer with the capacitor mounted on a test fixture that reflects actual use, hence, the designer might decide to de-embed this test fixture-added resistance and inductance before carrying a post-layout s-parameter extraction.

The DC bias effect in decoupling capacitors significantly influences their behavior in real-world applications, as shown in the first chart in the figure above. As a capacitor is subjected to a DC voltage, the electric field within its dielectric material can alter its effective capacitance. This effect is especially pronounced in multilayer ceramic capacitors (MLCCs), where the dielectric material's properties are sensitive to the applied voltage. Higher DC bias levels can cause a substantial reduction in capacitance, particularly in capacitors using class II or III dielectrics like X7R or Y5V. Thus, the capacitor parameters to be used in the simulations should take this DC bias derating into consideration.

Inductors

Ideal inductors are theoretical components with perfect linear behaviour, zero resistance, and no parasitic capacitance or electromagnetic interference. They maintain a consistent inductance value across all frequencies and current levels. In contrast, actual inductors exhibit non-ideal characteristics such as series resistance (DCR), frequency-dependent inductance, saturation at high current levels, and parasitic elements that alter their performance. These deviations must be carefully modeled and accounted for in PDN simulations; for example, simulating a large signal current pulse with a constant inductance element is usually inaccurate since the inductance value is current-dependent in actual operation, as shown in the first chart of the figure below. Coilcraft, a popular vendor of PCB inductors and transformers, offers multiple models for the same part based on the type of simulation to be carried out (impedance models, saturation models, power efficiency models, etc.). Choosing the right inductor model for SPICE simulation becomes a necessity [5].

Electromagnetic Coupling between PDN Components

Electromagnetic shielding for inductors and transformers on a printed circuit board (PCB) is critical for mitigating electromagnetic interference (EMI) and minimizing noise coupling. Shielding materials, such as ferrite or conductive enclosures, help contain magnetic flux within a limited space and reduce emissions [6]. For inductors, shields made of low-resistance metals like copper and aluminum confine the electric fields and also prevent magnetic flux passage at high frequencies. Meanwhile, at low frequencies, high-permeability magnetic materials are used. In transformers, electrostatic shielding can isolate the primary and secondary windings, improving signal integrity and reducing leakage inductance. Effectiveness depends on material properties, shielding geometry, and operational frequency.

Although shielding effectiveness for PCB inductors and transformers is critical for mitigating EMI and minimizing noise coupling, it is often hard to provide models for PDN designers to include these coupling effects in their analysis. Hence, good layout design practices should be adhered to, and these components should be physically separated on the PCB.

In a nutshell, know the limitations and the use cases of the component model you use before running simulations and drawing conclusions.

1- Static IR-Drop and Current Density Analysis

The objectives of the DC IR-drop analysis are: to ensure that the voltage drop across the PCB power planes and the ASIC package power planes does not exceed the minimum voltage specification, especially at hot temperatures. In addition, the current density should never exceed the maximum current density that can be handled by the PCB or the ASIC copper without running into thermal issues. Finally, the VRM sense line location and the output voltage setting can be fine-tuned with the knowledge of the PDN IR drop budget.

DC IR-Drop Simulation of the ASIC Package and the PCB Layouts

This is probably the first power integrity analysis that is typically done at the beginning for both the PCB and the ASIC package. Some tools like ANSYS Siwave can merge the package and the PCB stackups into one project. The simulation proceeds as follows:

• The ASIC or the PCB layout file is imported to a tool like ANSYS Siwave or Cadence Sigrity PowerDC.
• In the case of PCB simulation, voltage sources are applied to where the VRM is expected to sit and current sinks are applied at the BGAs. The value of the current per bump should be obtained from the ASIC's intellectual property (IP) designer.
• In the case of ASIC simulation, voltage sources are applied to the BGAs and current sinks are applied at the bumps.
• The IR drop analysis is run at maximum laminate temperature (a value that should be concluded from thermal simulations). High current density regions are identified and re-optimized.

DC IR-Drop Simulation of the Die

The same DC IR-drop analysis is run on the die using a tool like ANSYS Redhawk-SC. High current density spots as well as excessive resistance paths can be pointed out and the silicon design should be fixed as needed. 

Putting all Together in the PDN Schematic

The total IR drop is the combination of the drop due to VRM resistance, PCB power planes, package routing, and the on-die path resistance to the load. A simple spice tool such as LTSpice can calculate the voltage delivered to the sink. This analysis should be done for all power rails and load currents. If more than one load is sharing the same power planes, then the analysis should be done with all of these loads running together to determine the worst-case current density and IR drop.

In a nutshell, the designer should make sure there is enough copper for all the load currents working simultaneously.

2- AC Harmonic Analyses

The objective of AC sweeps is to quickly identify both resonances in power rails and significant coupling between these rails. These sweeps serve as preliminary checks to explore the AC characteristics of the power delivery network. The S-parameters of the power planes in the ASIC package and the PCB layouts are extracted for the power rails under investigation using a finite element analysis (FEA) tool like ANSYS Si-Wave. These S-parameters are then imported into a schematic tool, such as Keysight ADS or ANSYS Circuit, to construct a power delivery network model that spans from the voltage regulator module (VRM) to the load. The model should incorporate AC models for the VRM, broadband decoupling capacitor models, and the die impedance, which are added to the circuit.

S-parameters Extraction

The procedure of accurate S-parameter extraction for either the PCB or the ASIC package that is recommended by Teramesh is as follows:

• The layout file is loaded into the FEA solver (ANSYS Si-wave or similar), and stack-up parameters (such as layer thicknesses, conductivity, dielectric constant and loss tangent) are input to the simulator
• BGAs and Bumps that belong to the same power rail and are connected to the same on-die current sink may be grouped together (i.e. connected with a perfect electrical conductor) to simplify the s-parameter file.
• PCB and package capacitors are modeled with their derated values as per the applied voltage. A web-tool like Murrata Simsurfing is a very good resource to identify derating curves.  Teramesh prefers the use of an RLC model to S-parameter models to ensure the DC point is accurately modeled.

• The capacitors can be included in the S-parameter extraction to minimize the number of ports unless further tuning of these capacitor values is needed. On the other hand, inductors and ferrite beads behave non-linearly as per the current flowing into them. It is recommended to expose them during extraction (keep ports where these components are, then add a non-linear model in the schematic simulation).

• Circuit ports are applied to the ends of the power planes (i.e. at the BGA and the bump for an ASIC package simulation, or at the VRM input and the BGA for a PCB simulation), and port impedances are set to a small value (0.01Ω or similar).
• The analysis is run from DC to multiples of the maximum switching frequency of the power load inside the ASIC.

Chip Power Model and Die Impedance Model

ANSYS Redhawk-SC and many other integrated circuit CAD tools can extract both a time-domain current signal that mimics the device's real current withdrawal (current profile or chip power model) and a spice model to represent the impedance and the on-die capacitance between the bump and the switching element (Die Impedance Model). It is crucial to include the die impedance model in the simulation to reflect the real device performance at the GHz frequency range. The chip power model will be used in the transient simulation in the next section.

Small Signal Harmonic Analysis

With the power plane S-parameters and the die impedance models available, the power integrity designer constructs a schematic simulation bench, wiring all components as shown in the figure below. A harmonic AC source with a small amplitude (e.g., 1 µA) is assigned to each power rail. The S-parameter files should capture the coupling between these power rails. In the simulation, one current source is activated at a time, and the load voltage versus frequency curve is plotted. This curve is then inspected for unwanted resonances and compared against the ripple masks (or target impedance) provided by the IP designer. The ripple voltage induced on a voltage rail when the other is activated is a good assessment of the isolation between the two rails.

In a nutshell, group the power pins of the ASIC reasonably to mimic real operation, use broadband capacitor, beads and inductor models, then search for real resonances.

3- Dynamic IR-Drop Transient Analysis

After the AC harmonic analysis identifies PDN resonances and coupling issues, and the designs are adjusted accordingly, a time-domain verification is performed using the actual device switching current model. This step ensures the proper operation of the ASIC under real operating conditions. The time-domain simulation verifies both the device's on/off and steady-state current profiles. A PDN schematic model, similar to the one used in the AC harmonic analysis, simulates the PDN with a real-time chip current signal. The current profile versus time (chip power model) and the die impedance model are extracted and imported into the schematic simulation tool as inputs for the circuit. The voltage at the die load point is then analyzed against the ripple specifications in both the time and frequency domains. The voltage is first observed in the time domain versus the maximum and minimum values allowed for the power rail, and then the fast Fourier transform of the dataset is compared against the AC ripple masks.

Power On/Off Current Profiles - Rising/Falling Edge Analysis

The step load from powering on/off the device results in the highest rate of change of current, which yields high voltage ringing (ripple) at the load point. The ripple increases as the inductance between the VRM and the load increases. If the current profile is unavailable, the on/off waveform can be approximated with a piecewise linear (PWL) function of a realistic rise/fall time. Since the step response involves a large change in the current value, a current-dependent model for series inductors/beads on the simulated power rail is highly recommended to ensure accuracy. The VRM set point can also be tuned so that the voltage ripple meets the specification.

Steady State Current Profiles - High Frequency Analysis

ASIC CAD tools can also predict the steady state current profile for each of the device operation modes, which usually involves high frequencies since this is the current withdrawn by device clocks, RF inputs/outputs, and high-speed digital interfaces. This means the timestep used for the transient simulation should be too small (picoseconds). The same simulation setup of the step load response can be re-used to calculate the steady-state ripple by changing the time step and the current profiles only.

Worst Case Current Profiles - Forced Step Response

If representative current profiles were not available for the power integrity analysis, a periodic-step current load of the same fundamental frequency as the PDN resonant peaks can be used to test the limits of the power rail ripple. This results in the worst-case time domain ringing and imposes tight PDN design targets. Teramesh does not recommend this worst-case analysis approach since it usually results in higher-cost PDN designs. Instead, the CPM-based approach results in a balanced PDN design between cost and performance.

In a nutshell, verify the ripple performance across frequency for the worst operational case.

Summary

In this article, we explored Teramesh's PI analysis methodology, and we drew important conclusions for each phase in the PI flow:

• Be aware of the limitations of the simulation models used for each component of the PDN before concluding.
• Carry out the DC IR Drop analysis at maximum temperature, and make sure there is enough copper on both: the PCB and the ASIC package, while all the load currents are working simultaneously.
• In the AC harmonic analysis, group the power pins of the ASIC reasonably to mimic real operation, use broadband capacitor models (such as series RLC model), beads and inductor models, then look for real resonances and coupling in the frequency responses of the voltage rails at the die.
• Finally, verify the ripple performance across frequency for the worst operational case through a transient analysis.

References

    [1]    Larry Smith and Eric Bogatin, "Principles of power integrity for PDN design - Simplified", Prentice Hall Signal Integrity Library, 2017. ISBN-13: 978-0-13-273555-1.

    [2]    Sandler, S., Dannan, B., Barnes, H., and Yots, C., "VRM Modeling and Stability Analysis for the Power Integrity Engineer," DesignCon 2023, Santa Clara, CA, 2023.

    [3]    Dannan, B., "Power Integrity Unleashed: Navigating State-Space Average VRM Models for Robust Simulation Designs - Part I," Signal Edge Solutions, 2023.

    [4]    Kumar, S., and Singh, B., "State-Space Modeling, Design, and Analysis of the DC-DC Converters for PV Application: A Review," Sustainability, vol. 16, no. 1, p. 202, 2023. https://doi.org/10.3390/su16010202

    [5]    Coilcraft, "Simulation Model Considerations: Part I," Coilcraft, Cary, IL, 2023. [Online]. Available: https://www.coilcraft.com/en-us/models/howto/simulation-model-considerations-part-i/.

    [6]    Ott, H. W., Electromagnetic Compatibility Engineering, Hoboken, NJ: Wiley, 2009.