Signal Integrity Analysis Methodology for Printed Circuit Boards

The purpose of this article is to provide an overview of Teramesh's methodology for conducting signal integrity (SI) analysis for a printed circuit board (PCB) project. This article also serves as a guideline for SI designers planning a new project. It can be used as a reference for technical leaders expecting SI design results or for project managers planning timelines and monitoring project execution. Additionally, hiring managers can use it to evaluate candidates for SI designer roles. Broadly, the article outlines a framework for the SI activities necessary for any PCB with high-speed interfaces.

The Goal of the Signal Integrity Analysis

What is the value of a precise and well-modeled simulation that reveals poor design performance but is completed after the design has been sent for manufacturing? Is it time-efficient to finalize the routing of a PCB layout only for the SI engineer to discover through post-layout simulations that the performance is poor and the board needs to be redone? Of course not. The value of SI analysis is significantly enhanced when performed earlier in the design phase to avoid project delays and unnecessary design iterations.

At Teramesh, we adopt a "Shift-Left" SI design approach—a term borrowed from software development, where early testing in the development cycle is emphasized. Similarly, in hardware development, the bulk of SI analysis should occur early, even before the PCB layout begins. This ensures adequate time to incorporate simulation findings into the design without delays. Our approach focuses on deriving a set of design constraints that guide the layout design process, ensuring that the first iteration of the PCB layout meets the required SI performance. Post-layout verifications are reserved only for situations where they are necessary.

In essence, the SI Engineer’s role is to guide the layout designer proactively, NOT wait for post-layout verifications.

The SI workflow for a PCB involves the following steps:

1. PCB material modelling
2. Transmission line and 3D structure optimizations
3. Design the channel topology (Prelayout simulations)
4. Post-layout analysis (as needed)
5. Correlation to the lab measurements

The following sections detail these steps and provide real-world examples from past projects.

1- PCB Material Modeling

The first, often overlooked step in SI analysis is accurately modeling PCB material parameters: dielectric constant (D_K or ɛ_r), dielectric loss tangent (D_F or Tanδ), smooth copper resistivity, and copper surface roughness. Engineers often rely on textbook or datasheet values for these parameters without an in-depth understanding of how these values were measured, which can lead to simulation results that deviate significantly from lab measurements. Incorrect material parameters can introduce errors throughout the SI workflow.

Dielectric Constant

PCB dielectrics consist of layer(s) of glass fibers embedded in resin. The dielectric constant depends on the glass-to-resin ratio, the direction of the electric field relative to the fiber, the measurement frequency, and the substrate temperature.

• Glass to resin ratio
  If D_K,glass = 5~7 and D_K,resin = 2~4 [1],  laminates with more fibers often have higher effective dielectric constants than those with more resin.

• Direction of the electric field
  In-plane fields experience the glass fibers parallel to the resin, while out-of-plane fields experience them in series. For example, the electric field lines in a single-ended stripline will be normal to the glass fibers, and hence a series mixing rule should be used:

h / D_{K,out-of-plane} = h_Glass / D_K,Glass + (h - h_Glass) / D_K,Resin  (1)

Meanwhile, for the electric field lines around a via barrel are parallel to the glass fibers, and hence a parallel mixing rule should be used to calculate the effective in-plane dielectric constant: 

The in-plane dielectric constant is usually characterized using a split-post cavity resonator (IPC-TM-650 2.5.5.13), while the out-of-plane value is obtained from a stripline resonator or a parallel plate capacitor (IPC-TM-650 2.5.5.5 or 2.5.5.9, respectively). When Dk is measured by an in-plane method, effective Dk is linear to resin content for a given glass style [1]. Therefore, by linear fitting of the D_K,in-plane values of the same glass weave versus the resin content (RC) (usually provided in datasheets), the D_K,glass and D_K,resin can be calculated by simple algebra.

D_K,glass = y-intercept                 (3)

D_K,resin = slope x 100% + D_K,glass  (4)

It is important to note that many simulation tools do not support dielectric constant anisotropy, and hence the user will have to provide the appropriate value (i.e in-plane or out-of-plane D_k) manually using equations (1) and (2).

• Frequency and temperature
  The dielectric constant (D_k) decreases with frequency and increases as the temperature is raised. The processes of extracting the D_k across frequency is beyond the scope of this article, yet it should be highlighted that most simulation tools use the Djorovic-Sarkar dielectric frequency dependence model. In any case, the frequency dependence has to be set in the simulator such that it is as close as possible to measured data. As for the temperature, we did not come across a simulation tool that accounts for the temperature dependence of the dielectric constant automatically. Therefore, the user should do this manually by creating multiple copies of the same material model for each temperature of interest.

Loss Parameters: Dielectric Loss Tangent and Conductor Loss (Smooth Copper Resistivity & Copper Surface Roughness)

The loss of a PCB trace is due to the dielectric loss tangent as well as the conductor loss. The latter is further divided into smooth and rough copper losses. There exist mathematical procedures to decompose the measured total insertion loss of a stripline into those three loss components  [2], [3].

Another approach is to obtain the dielectric loss tangent, which can be measured (by the manufacturer or in-house) and provided to the SI designer. The loss tangent increases with the temperature and frequency of operation, which has to be input correctly to the simulation tool. The conductor loss has two components: the copper resistivity, which depends on temperature (smooth copper loss) and is an easy parameter to obtain. In addition, due to the treatment done to increase the adhesion between the copper foil and the dielectric material, the copper surface becomes rough, which results in additional frequency-dependent loss due to the skin effect. It should be highlighted that each simulator we came across has different surface roughness models. Therefore, the SI designer should make sure to correlate the roughness loss to the simulator across frequency regardless of the model used.

When all of those three loss components are modelled precisely in the simulator, we should make sure that the total loss of a stripline per inch matches the measured value or the value provided by the PCB manufacturer. Teramesh recommends creating correlation simulation test benches of 1-inch trace and verifying the loss parameters yield the provided dB/inch.

In a nutshell, use accurately measured dielectric and copper foil parameters, then feed them properly into the simulator you use.

2- Optimize Transmission Lines and Signal Discontinuities

After the material model has been perfected, we design the building blocks of the PCB channels: transmission lines, via transitions, SMD components, and connector and IC breakouts. Finite Element Analysis (FEM) is done in 2D or 3D to calculate trace impedances, via geometries, and optimize complex 3D structures which will be used on the PCB.

Stripline Impedance

Use a 2D FEM solver tool like Polar Si9000 Quick Solver or Hyperlynx 2D Field Solver to design: single-ended and differential striplines. Polar offers a convenient way to add manufacturer tolerances for every material parameter and structure dimension, while Hyperlynx enables the creation of complex custom multi-layer structures easily. Whichever is available or more convenient, the SI designer should be able to come up with a set of trace widths and P/N spacings that achieve the required characteristic impedances. Provide multiple designs for each transmission line; optimize once for total loss (call it the low-loss design), and another for cross section area (will be used for breakouts or trace necking).

Microstrip & Co-planar Waveguide Impedance

Here, we recommend Polar Si8000/9000 as it offers maximum flexibility in configuring solder mask parameters. Like in the stripline case, include all manufacturing tolerances, and provide multiple designs for each transmission line; optimize total loss once, and another for cross section area.

Trace-to-Trace Spacing

After the microstrips and striplines have been designed and optimized, the minimum signal-to-signal separation should be simulated to provide crosstalk isolation guidelines for the PCB layout. Typically, system designers set a target of 40~60dB of isolation for high-speed digital signals and 60~80dB of isolation for sensitive signals (like clock nets or RF traces). An example of a simple simulation schematic in a tool like Hyperlynx is shown in Figure 3. The distance between the two differential pairs is swept, and the cross-coupling S-parameters are plotted; the minimum separation that yields an s-parameter value of the target isolation is chosen.

Via Transitions

Teramesh recommends ANSYS HFSS and HFSS 3D Layout for the optimization of via transitions for single and differential-ended high-speed digital and RF signals. For broadband applications, usually, the antipad size is the parameter to tune the via return loss. Sometimes, when the antipad is too large, the trace width above the antipad helps smooth the TDR impedance plot. The antipad sizes on different layers of the PCB can be tuned individually for finer optimization. Teramesh also recommends following the optimization with a sensitivity or a statistical analysis for manufacturing tolerances, such as via hole registration, layer thickness tolerance, stub length variation, and dielectric constant uncertainty. This helps ensure that the design is statistically robust.

Voids under SMD Pads

SMD components placed along the high-speed signal path create unwanted capacitance with the ground planes beneath their pads. Therefore, adding voids under those pads on the ground layer helps improve the overall return loss of the channel via smoothing the impedance profile. The void shape and size can be optimized in HFSS 3D Layout by sweeping the void size and plotting the TDR and Return loss responses.

Connectors

Similar to SMD components, SMD connectors benefit from optimizing voids underneath their pads as well as the overall trace geometry of the fanout section. It is highly recommended to obtain a 3D model for the connector from the vendor and include it in an end-to-end 3D simulation to capture and eliminate any unwanted resonance that might arise when the connector is mounted on the PCB. ANSYS HFSS is best suited for these simulations.

Microwave Transitions (Vias and Connectors)

PCB vias and connectors fail to achieve good broadband return loss above 20GHz. Therefore, in microwave applications of frequencies > 20GHz, return loss can be significantly improved through open stub matching, which matches the impedance of the via or the connector to the trace on the PCB in the specific frequency range of operation only. Designs often include a single stub or double stub. The stub(s) geometry and location relative to the via or connector to be matched are optimized in ANSYS HFSS or HFSS 3D Layout, and return loss is plotted in the operating frequency band. Teramesh strongly recommend doing sensitivity analysis for the chosen stub matched design to ensure adequate performance statistically with manufacturing variations. Figure 5 shows an example of a double stub matched RF transition with performance optimized around 15.5GHz, yielding a return loss better than -30dB.

In a nutshell, minimise the impedance discontinuities along the signal path for the frequencies of operation.

3- Design the Channel Topology (Prelayout Simulations)

After the channel's building blocks (traces, vias, connectors, etc.) have been created and optimized, the routing topology is designed, simulated, and compared to the specifications masks. This phase answers questions such as:

• How many via transitions can be accommodated in a specific high-speed link?
• What is the maximum trace length for a given interface?
• Should certain links be routed with trace impedance lower than 100Ω?
• Will we need a retimer for the PCIe 5 interface?

In this section, we will consider the case of a 32Gbps PCIe Gen 5 interface as an example for the SI work flow. This process flow can be applied to all other high-speed and interfaces and clock signals with on-PCB termination.

Insertion Loss Budgeting and Return Loss Analysis

We know that PCIe Gen 5 dedicated only 16dB of insertion loss at 16GHz for the system base board from the PCIe Base Specification. We also know we need a minimum of 2 via transitions at the ASIC breakouts to route those channels as striplines (which we optimized and simulated for insertion loss and return loss). We also concluded the loss per inch of the striplines in the previous step. Consequently, the SI designer can announce:

maximum trace length (inch) = (16dB allowed loss - 2x dB loss per via) / (stripline loss per inch)

The team can now decide whether they need a retimer for this link (such an expensive component on the board has to be justified with calculations and simulations). This process can be applied to all high-speed interfaces, and the maximum trace length for these interfaces can be concluded and shared with the layout designer. The topology should be created in a schematic tool like ANSYS Circuit, Keysight ADS, or HyperLynx SI/PI to obtain precise values. The SI designer can further experiment with options like adding more via transitions to the signal path, different trace impedances, and different connector models and assess whether the insertion and return losses are still within limits.

Channel Compliance and IBIS-AMI Simulation

Furthermore, the schematic simulation bench can be expanded to include multiple PCIe channels going in parallel, with coupled transmission lines to investigate crosstalk levels. Constraints like maximum microstrip running length in breakout regions and minimum trace-to-trace separation can be calculated. Then, the channel s-parameters are exported and checked against compliance masks. Finally, the Serdes IBIS-AMI models can be added to the simulation to estimate the eye diagrams and the Serdes configuration parameters (like equalizer settings, transmitter amplitude, and receiver amplifier settings). The IBIS-AMI simulations should be done at all silicon process corners (Fast-Typical-Slow) and with PCB manufacturer tolerances. A tool like Hyperlynx SI/PI was found to be very helpful in running such batch simulations.

In a nutshell, know your silicon, budget carefully, and aim for a few dB above the specified masks to keep margin for the layout designer.

All the previous analyses should happen before the PCB layout starts. This is what we meant by a "Shift-left" SI analysis approach. The idea is to speed up the project execution and ensure the first attempt of the PCB layout will be successful.

4- Post Layout Simulations

The final PCB layout might deviate from the SI guidelines and design constraints provided by the pre-layout simulations. Therefore, Teramesh recommends doing post-layout verification for critical high-speed interfaces in general, especially whenever the PCB layout violates a constraint. This type of simulation serves as a final SI check for the layout. The process starts by importing the geometry to a 3D FEM solver like ANSYS HFSS 3D Layout, then extracting the S-parameters of the simulated PCB channels, then running the same pre-layout simulation benches with the extracted s-parameters instead.

Expensive Resources

It should be noted that a full 3D simulation of a PCB structure is a very resource-utilising process. Such simulations run on multi-processor servers, which are not free to use. SI designers should prioritize critical problems for post-layout simulations and optimize the use of company resources. Utilising solvers that make use of transmission line models to speed up the solution (such as ANSYS Si-wave or Hyperlynx SI/PI) makes a lot of sense in many cases. The Siwave solver of ANSYS HFSS 3D Layout offers flexibility and customizability to the user to choose what areas should be solved in full 3D mode and which areas can be accelerated by using the 2D solver. Teramesh recommends adding Siwave regions around vias, breakouts, and connector pins.

In a nutshell, check for critical interfaces, and whenever the layout violates the design constraints.

5- Correlation to the Lab Measurements

Correlating the simulation results to the lab measurement is a crucial step to generate more accurate simulation results in the future and, hence, allow your team to make better decisions. Passive correlation refers to measuring the copper on the PCB, while active correlation refers to measuring the silicon and comparing it to the IBIS model. Due to the usual time and budget limitations, the SI designer should carry out the passive correlation and may just ask the silicon vendor for the IBIS models correlation and quality reports.

Passive Correlation

Passive correlation is to measure and collect data from the actual manufactured PCB to generate or update simulation models. PCB characterisation structures such as long and short striplines of different characteristic impedances, microstrips, via stubs, and resonators are added to the PCB layout to be measured with a Vector Network Analyzer (VNA) or Time-Domain Reflectometer (TDR). Additionally, cross-section analysis enables the collection of manufacturing data like layer thicknesses, copper etch factors, and surface roughness. All of these data help extract the copper and dielectric material parameters to be utilised in future simulations.

In a nutshell, correlate stripline insertion loss to the simulation; magnitude and phase.

Summary

In this article, we explored Teramesh's SI analysis methodology, and we concluded tips for each phase in the SI flow:

• The SI engineer's role is to proactively guide the layout design, not only post layout verification.

• Use accurately measured dielectric and copper foil parameters, then feed them properly into the simulator.

• Minimize the impedance discontinuities, die to die, for the frequencies of operation.

• Know your silicon, budget carefully, and aim for a few dB above the specified masks to keep the margin for layout imperfections.

• Check for critical interfaces after they are routed and whenever the layout violates the design constraints.

• Correlate stripline insertion loss to the simulation, magnitude, and phase.

References

[1]   H. Zhou and W. Zhang, "PCB Laminate Material Out-of-plane Dielectric Constant Extraction Methodology," 2022 IEEE 26th Workshop on Signal and Power Integrity (SPI), Siegen, Germany, 2022, pp. 1-5, doi: 10.1109/SPI54345.2022.9874947.

[2]   Elaine Liew et al "Signal Transmission Loss due to Copper Surface Roughness in High-Frequency Region", IPC APEX EXPO Conference Proceedings – December 2013. ISBN:978-1-4799-2311-3

[3]   Atar Mittal, "Losses in PCB Transmission Lines", Online Article, March 2021.

[4]   "Layout Guidelines of PCIe® Gen 4.0 Application With the TMUXHS4412 Multiplexer", Application Report, SLAAE45 – September 2021.